2015-2016 Editorial Board

Editor-in-Chief

Krishnendu Chakrabarty

Associate Editor-in-Chief

Massimo Alioto
  • Massimo Alioto
  • Department of Electrical and Computer Engineering
  • National University of Singapore
  • Singapore 117583
  • malioto@ieee.org massimo.alioto@gmail.com
  • Ultra-low voltage digital circuits; Self-powered integrated systems; Approximate computing; Near-threshold processors, memories and specialized hardware; Emerging technologies

Associate Editor

Bevan Baas
  • Bevan Baas
  • Dept. of Electrical and Computer Engineering
  • University of California
  • Davis, CA 95616-5294
  • bbaas@ucdavis.edu
  • Many-core processors; DSP algorithms and architectures; Video and image processors; Programmable DSP architectures; Embedded processors

Associate Editor

Chye Chirin Boon
  • Chye Chirin Boon
  • Nanyang Technological Univ.
  • Singapore
  • ECCBoon@ntu.edu.sg
  • RF Receiver; RF Transmitter; Phase-locked Loop (PLL); Wireless IC; MMW IC

Associate Editor

Chip-Hong Chang
  • Chip-Hong Chang
  • School of Electrical and Electronic Engineering
  • Nanyang Technological University
  • Singapore
  • ECHChang@ntu.edu.sg
  • Residue Number Systems; Computer Arithmetic; Physical Unclonable Functions; Hardware Trojan Detection; Hardware Security

Associate Editor

Meng-Fan (Marvin) Chang
  • Meng-Fan (Marvin) Chang
  • Department of Electrical Engineering
  • National Tsing Hua University
  • Hsinchu, 30013
  • Taiwan
  • mfchang@ee.nthu.edu.tw
  • Memory circuits; Ultra low-voltage designs; Nonvolatile logics and processors; Computing-in-memory; Device and circuit interaction for emerging devices

Associate Editor

Naeuhyuck Chang
  • Naeuhyuck Chang
  • Korea Advanced Institute of Science & Technology
  • Daejeon, 305701
  • Korea
  • naehyuck@cad4x.kaist.ac.kr
  • System-level power estimation; Low-power system design; Embedded systems; Design automation of things; Energy harvesting systems

Associate Editor

Shih-Chieh Chang
  • Shih-Chieh Chang
  • Department of Computer Science
  • National Tsing Hua University
  • Taiwan 30013, R.O.C.
  • scchang@cs.nthu.edu.tw
  • Synthesis; Low power; Adaptive architecture

Associate Editor

Yao-Wen Chang
  • Yao-Wen Chang
  • Department of Electrical Engineering
  • National Taiwan University
  • Taipei, 10615
  • Taiwan
  • ywchang@ntu.edu.tw
  • Physical Design; Design for Manufacturability/Reliability; Analog Layout Design Automation; Package, Board, and Chip Design/Co-Design; Low Power Design

Associate Editor

Poki Chen
  • Poki Chen
  • Department of Electronic Engineering
  • National Taiwan University of Science and Technology
  • Taipei, Taiwan, R.O.C.
  • poki@mail.ntust.edu.tw
  • Smart temperature sensor; Time-to-digital converter; Digital-to-time converter; Phase-locked loop; Delay-locked loop

Associate Editor

Masud Chowdhury
  • Masud Chowdhury
  • Department of Computer Science and Electrical Engineering
  • University of Missouri
  • Kansas City, MO 64110-2499
  • masud@umkc.edu
  • On-chip Voltage Regulation; Subthreshold Design for Ultra Low Power Circuits; Noise, Timing, and Power Issues; 3D Integrated Circuits; 2D Nanomaterial based Devices and Circuits

Associate Editor

Pasquale Corsonello
  • Pasquale Corsonello
  • Department of Informatics, Modeling, Electronics and System Engineering (DIMES)
  • University of Calabria
  • Rende, Italy
  • p.corsonello@unical.it
  • Low-Power digital circuit design; VLSI circuits for image processing; Field Programmable Gate Arrays; Quantum Dot Cellular Automata circuits and architectures

Associate Editor

Ibrahim (Abe) Elfadel
  • Ibrahim (Abe) Elfadel
  • Institute Center for Microsystems (iMicro)
  • Masdar Institute of Science and Technology
  • Abu Dhabi, UAE
  • ielfadel@masdar.ac.ae
  • Power/thermal management of digital systems, 3D integration, High-speed interconnect, Low-power embedded DSP, Power-source integration, VLSI CAD, sensor-based architectures, and Internet of Things

Associate Editor

Said Hamdioui
  • Said Hamdioui
  • Department of Computer Engineering
  • Delft University of Technology
  • Delft, The Netherlands
  • S.Hamdioui@tudelft.nl
  • Memory test; 3D stacked IC Test; IC reliability; Memristor Technology; Hardware security

Associate Editor

Masanori Hashimoto
  • Masanori Hashimoto
  • Department of Info. Systems Eng.
  • Osaka University
  • Suita, Osaka 565-0871 Japan
  • hasimoto@ist.osaka-u.ac.jp
  • Low voltage circuit design; Design for reliability; Power integrity analysis; Timing analysis; Soft error modeling

Associate Editor

Tsung-Yi Ho
  • Tsung-Yi Ho
  • Dept. of Computer Science
  • National Chiao Tung University
  • Hsinchu, Taiwan 30010
  • tyho@cs.nctu.edu.tw
  • Design Automation and Optimization for Microfluidic Biochips; Automobiles; Energy Applications; Nanometer Integrated Circuits

Associate Editor

Yuh-Shyan Hwang
  • Yuh-Shyan Hwang
  • Department of Electronic Engineering
  • National Taipei University of Technology
  • Taipei, Taiwan, R.O.C.
  • yshwang@mail.ntut.edu.tw
  • Analog Ics; Mixed-signal Ics; Power management Ics; Sensor circuits; Low-voltage low-power VLSI circuits.

Associate Editor

Rajiv Joshi
  • Rajiv Joshi
  • IBM
  • Yorktown Heights, NY 10598
  • rvjoshi@us.ibm.com
  • Technology; FinFETs; Emerging devices; 3D; Variability; Reliability; VLSI Memories; SRAM; CAD aspect related to memory; Low power design; VLSI Circuits; Interconnects; Predictive Analytics

Associate Editor

Tanay Karnik
  • Tanay Karnik
  • Academic Research Office
  • Intel Corporation
  • Hillsboro, OR 97124
  • Tanay.Karnik@intel.com
  • Adaptive circuits; Switching converters; Cache memories; Radiation Hardening; Physical Design

Associate Editor

Mehran Mozaffari Kermani
  • Mehran Mozaffari Kermani
  • Department of Electrical and Microelectronic Engineering
  • Rochester Institute of Technology
  • Rochester, NY 14623
  • mmkeme@rit.edu
  • Hardware Security and Trust; VLSI Architectures for Computer Arithmetic; Cryptographic Hardware; Medical Devices Reliability and Security; Fault Diagnosis and Tolerance in Signal Processing

Associate Editor

Chulwoo Kim
  • Chulwoo Kim
  • Dept. of Electronics Engineering
  • Korea University
  • ckim@korea.ac.kr
  • PLL, DLL; Wireline transceiver (not wireless transceiver); Power management (DC-DC converter, LDO); ADC; Energy harvesting circuit

Associate Editor

Tony Tae-Hyoung Kim
  • Tony Tae-Hyoung Kim
  • School of Electrical and Electronic Engineering
  • Nanyang Technological University
  • Singapore 639798
  • thkim@ntu.edu.sg
  • approximate computing; ultra-low power digital circuits; ultra-low voltage circuits; memory circuits; circuit reliability

Associate Editor

Jaydeep Kulkarni
  • Jaydeep Kulkarni
  • Intel Corp.
  • Hillsboro, OR 97124 USA
  • Jaydeep.p.kulkarni@intel.com
  • Memory; Low-voltage design; Energy-efficiency; Resiliency; Power-management

Associate Editor

Eren Kursun
  • Eren Kursun
  • Department of Computer Science
  • Columbia University
  • New York, NY 10027
  • erenkursun@ieee.org
  • Low Power Design; Emerging technologies; 3D Integration; Embedded Systems, VLSI Architectures; FPGA design

Associate Editor

Erik Larsson
  • Erik Larsson
  • Dept. of Electrical & Information Technology
  • Lund University
  • Lund, 22100 Sweden
  • erik.larsson@eit.lth.se
  • Test planning, System test, Standards for test, Fault-tolerance, Stacked chip testing

Associate Editor

Hai Li
  • Hai Li
  • Dept. of Electrical & Computer Engineering
  • University of Pittsburg
  • Pittsburgh, PA 15261 USA
  • hal66@pitt.edu
  • Memory design and architecture; Neuromorphic computing; Device modeling; Low power design

Associate Editor

Huawei Li
  • Huawei Li
  • Institute of Computing Technology,
    Chinese Academy of Sciences
  • Beijing 100190, China
  • lihuawei@ict.ac.cn
  • Digital circuit testing; Design verification; Hardware security; Design for reliability; Approximate computing

Associate Editor

Mohammad Mansour
  • Mohammad Mansour
  • Department of Electrical and Computer Engineering
  • American University of Beirut
  • Beirut, Lebanon
  • mm14@aub.edu.lb
  • MIMO OFDM; LDPC/turbo codes; Nanoscale computing systems; Error-resilient architectures; Capacity-approaching channel coding

Associate Editor

Syoichi Masui
  • Syoichi Masui
  • Fujitsu Laboratories
  • Kawasaki, Kanagawa, Japan
  • masui.shoichi@jp.fujitsu.com
  • Wireless transceiver; Wireless sensor network; Analog signal conditioning; Low-power analog design; Mixed-signal design

Associate Editor

Patrick Mercier
  • Patrick Mercier
  • Electrical and Computer Engineering
  • University of California, San Diego
  • La Jolla, CA 92093
  • pmercier@ucsd.edu
  • RF circuits, Energy harvesting; Switched-capacitor dc-dc converters; Energy management; Low-power design

Associate Editor

Prabhat Mishra
  • Prabhat Mishra
  • Department of Computer & Information Science & Engineering
  • Univ. of Florida
  • Gainesville, FL 32611 USA
  • prabhat@cise.ufl.edu
  • Embedded Systems; System-level Verification; Post-Silicon Validation and Debug; Energy-aware Computing; Hardware Security and Trust

Associate Editor

Makoto Nagata
  • Makoto Nagata
  • Graduate School of System Informatics
  • Kobe University
  • Kobe, Japan
  • nagata@cs.kobe-u.ac.jp
  • Mixed signal VLSI design; Hardware security; 3D IC; Power supply integrity; Electromagnetic compatibility

Associate Editor

Arun Natarajan
  • Arun Natarajan
  • School of Electrical Engineering and Computer Science
  • Oregon State University, Corvallis
  • Corvallis, Oregon 97331-5501
  • nataraja@eecs.oregonstate.edu
  • millimeter-wave, RFIC, RF energy harvesting, wireless transceivers, phased arrays

Associate Editor

Koji Nii
  • Koji Nii
  • Renesas Electronics Corporation
  • Tokyo 187-8588, Japan
  • koji.nii.uj@renesas.com
  • SRAM; Register file; Cache; Content Addressable-Memory (CAM); Low-power

Associate Editor

Steve Nowick
  • Steve Nowick
  • Dept. of Computer Science
  • Columbia University
  • New York, NY 10027 USA
  • nowick@cs.columbia.edu
  • Asynchronous circuits and systems; Networks-on-chip; Low-power digital design; GALS systems; Logic synthesis

Associate Editor

Partha Pande
  • Partha Pande
  • Computer Engineering School of EECS
  • Washington State Univ.
  • Pullman, WA 99164-2752 USA
  • pande@eecs.wsu.edu
  • Network-on-Chip; Multicore; Power Management; 3D Integration; Hardware Accelerato

Associate Editor

Sachin Sapatnekar
  • Sachin Sapatnekar
  • Dept. of Electrical & Computer Engineering
  • University of Minnesota
  • Minneapolis, MN 55455 USA
  • sachin@umn.edu
  • Aging/reliability; Timing; Logic optimization; Physical design; Spintronics

Associate Editor

Ioannis Savidis
  • Ioannis Savidis
  • Department of Electrical and Computer Engineering
  • Drexel University
  • Philadelphia, PA 19104
  • isavidis@coe.drexel.edu
  • High performance digital and mixed-signal integrated circuit design; 3-D integrated circuits; Electrical and thermal modeling; Power and clock delivery; Hardware security

Associate Editor

Aida Todri-Sanial
  • Aida Todri-Sanial
  • Microelectronics Department
  • CNRS-LIRMM/University of Montpellier
  • Montpellier, France 34095
  • aida.todri@lirmm.fr
  • Physical design; Low-power design; Emerging technologies (i.e. 3D, carbon nanotubes, etc.); Device and circuit reliability; Electro-thermal simulation

Associate Editor

Mingoo Seok
  • Mingoo Seok
  • Electrical Engineering
  • Columbia University
  • New York, NY 10027
  • ms4415@columbia.edu
  • Process-variation/thermal/aging adaptive circuits; Near/sub-threshold voltage circuits; Machine-learning hardware

Associate Editor

Sheldon Tan
  • Sheldon Tan
  • Department of Electrical and Computer Engineering
  • University of California at Riverside
  • Riverside, CA 92521
  • stan@ece.ucr.edu
  • Analog/mixed-signal circuits; Signal/power integrity; Thermal and reliability model and optimization; Parallel analysis

Associate Editor

Mark Tehranipoor
  • Mark Tehranipoor
  • Dept. of Electrical and Computer Engineering
  • University of Florida
  • Gainesville, FL 32611-6200
  • Tehranipoor@ece.ufl.edu
  • Hardware Security and Trust; Reliable Circuit Designs; VLSI Testing

Associate Editor

Miroslav Velev
  • Miroslav Velev
  • Aries Design Automation
  • Chicago, IL 60618
  • mvelev@gmail.com
  • Formal Verification; Boolean Satisfiability (SAT); Constraint Satisfaction Problem and Combinatorial Problems; Reconfigurable Architecture Design and Formal Verification; Microprocessor Design and Formal Verification

Associate Editor

Xiaoqing Wen
  • Xiaoqing Wen
  • Dept. of Creative Informatics
  • Kyushu Institute of Technology
  • Fukuoka 820-8502, Japan
  • wen@cse.kyutech.ac.jp
  • Power-Aware Testing; Automatic Test Pattern Generation (ATPG); Design for Testability (DFT); Fault Diagnosis; Built-In Self Test (BIST)

Associate Editor

Jiang Xu
  • Jiang Xu
  • Department of Electronic and Computer Engineering
  • Hong Kong University of Science and Technology
  • Clear Water Bay, Kowloon, Hong Kong SAR
  • jiang.xu@ust.hk
  • MPSoC; NoC; HW/SW Codesign; Optical/Photonic Interconnects; Reliability

Associate Editor

Wei Zhang
  • Wei Zhang
  • Dept. of Electronic & Computer Engineering
  • Hong Kong Univ. of Sci. & Technology
  • New Territories, Hong Kong China
  • wei.zhang@ust.hk
  • Reconfigurable computing; FPGA-based design; Thermal and power management; Electronic design automation; Emerging technologies

Associate Editor

Zhengya Zhang
  • Zhengya Zhang
  • Electrical Engineering and Computer Science
  • University of Michigan, Ann Arbor
  • Ann Arbor, MI 48109-2122 USA
  • zhengya@umich.edu
  • Digital communication systems,; Digital signal processing systems; Neuromorphic computing; Application-specific architecture, Error resilience

Editorial Assistant

Stacey Weber Jackson
  • Stacey Weber Jackson
  • Dept. of Electrical Engineering
  • Princeton University
  • Princeton, NJ 08544
  • tvlsiadm@princeton.edu